ISP1362BDTM

Product Summary

The ISP1362BDTM is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller integrated with the advanced Philips Slave Host Controller (PSHC) and the Philips ISP1181B device controller (DC). The USB OTG controller is compliant with On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a. The host and device controllers are compliant with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1362BDTM has two USB ports: port 1 and port 2. Port 1 can be hardware configured to function as a downstream port, an upstream port or an OTG port whereas port 2 can only be used as a downstream port. The OTG port can switch roles from host to peripheral, or from peripheral to host. The OTG port can become a host through the Host Negotiation Protocol (HNP) as specified in the OTG supplement.

Parametrics

ISP1362BDTM absolute maximum ratings: (1)supply voltage, VCC: -0.5 +4.6V; (2)input voltage, VI: -0.5 +6.0V; (3)latch-up current VI < 0 or VI > VCC, Ilu: 100mA; (4)electrostatic discharge voltage, ILI < 1 μA, Vesd: -2000 +2000V; (5)storage temperature, Tstg: -60 +150℃.

Features

ISP1362BDTM features: (1)Complies fully with: Universal Serial Bus Specification Rev. 2.0; On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a; (2)Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); (3)Adapted from Open Host Controller Interface Specification for USB Release 1.0a; (4)USB OTG: Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG dual-role devices; Provides status and control signals for software implementation of HNP and SRP; Provides programmable timers required for HNP and SRP; Supports built-in and external source of VBUS; Output current of the built-in charge pump is adjustable by using an external capacitor; (5)USB host: Supports integrated physical 4096 bytes of multiconfiguration memory; Supports all four types of USB transfers: control, bulk, interrupt and isochronous; Supports multiframe buffering for isochronous transfer; Supports automatic interrupt polling rate mechanism; Supports paired buffering for bulk transfer; Directly addressable memory architecture; memory can be updated on-the-fly; (6)USB device: Supports high performance USB interface device with integrated Serial Interface Engine (SIE), buffer memory and transceiver; Supports fully autonomous and multiconfiguration DMA operation; Supports up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints; Supports integrated physical 2462 bytes of multiconfiguration memory; Supports endpoints with double buffering to increase throughput and ease real-time data transfer; Supports controllable LazyClock (110 kHz ±50 %) output during suspend; (7)Supports two USB ports: port 1 and port 2: Port 1 can be configured to function as a downstream port, an upstream port or an OTG port; Port 2 can be used only as a downstream port; (8)Supports software-controlled connection to the USB bus (SoftConnect); (9)Supports good USB connection indicator that blinks with traffic (GoodLink); (10)Complies with USB power management requirements; (11)Supports internal power-on and low-voltage reset circuit, with possibility of a; (12)software reset; (13)Supports operation over the extended USB voltage range (4.0 V to 5.5 V) with 5 V tolerant I/O pads; (14)High-speed parallel interface to most CPUs available in the market, such as Hitachi SH-3, Intel StrongARM Philips XA, Fujitsu SPARClite, NEC and Toshiba MIPS, ARM7/9, Motorola DragonBall and PowerPCTM Reduced Instruction Set Computer (RISC): 16-bit data bus; 10 Mbyte/s data transfer rate between the microprocessor and ISP1362; (15)Supports Programmed I/O (PIO) or Direct Memory Access (DMA); (16)Supports suspend and remote wake-up; (17)Uses 12 MHz crystal or direct clock source with on-chip Phase-Locked Loop (PLL) for low Electro-Magnetic Interference (EMI); (18)Operates at +3.3 V power supply; (19)Operating temperature range from -40℃to +85℃; (20)Available in 64-pin LQFP and TFBGA packages.

Diagrams