TMS320C44PDB50

Product Summary

The TMS320C44PDB50 is a 32-bit, digital signal processor, manufactured in 0.72-mm double-level-metal CMOS technology. The TMS320C44PDB50 is part of the TMS320C4x generation of DSPs from Texas Instruments. The on-chip parallel-processing capabilities of the C44 make the immense floating-point performance required by many applications achievable.

Parametrics

TMS320C44PDB50 absolute maximum ratings: (1)Supply voltage range, VDD: -0.3 V to 7 V; (2)Input voltage range: -0.3 V to 7 V; (3)Output voltage range: - 0.3 V to 7 V; (4)Operating case temperature range, TC: 0℃ to 85℃; (5)Storage temperature range, Tstg: - 55℃ to 150℃.

Features

TMS320C44PDB50 features: (1)Highest performance floating-point digital signal processor (DSP): TMS320C44-60: 33-ns instruction cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M bytes/s; TMS320C44-50: 40-ns instruction cycle time; (2)Four communication ports; (3)Six-channel direct memory address (DMA) coprocessor; (4)Single-cycle conversion to and from IEEE-754 floating-point format; (5)Single cycle, 1/x, 1/√￣x; (6)Source-code compatible with 320C3x and 320C4x; (7)Single-cycle 40-bit floating-point, 32-bit integer multipliers; (8)Twelve 40-bit registers, eight auxiliary registers, 14 control registers, and two timers; (9)IEEE-1149.1+(JTAG) boundary-scan compatible; (10)Two identical external data and address buses supporting shared memory systems and high data-rate, single-cycle transfers: high port-data rate of 120M bytes/s; 128M-byte Program/data/peripheral address space; memory-access request for fast, intelligent bus arbitration; separate address-bus, data-bus, and control-enable pins; four sets of memory-control signals support different speed memories in hardware; (11)304-pin plastic quad flatpack (PDB Suffix); (12)Fabricated using 0.72-mm enhanced performance implanted CMOS (EPICTM) technology by texas instruments (TITM); (13)Separate internal program-, data-, and dma-coprocessor buses for support of massive concurrent i/o of program and data, thereby maximizing sustained CPU performance; (14)IDLE2 clock-stop power-down mode; (15)Communication-port-direction pin; (16)On-chip program cache and dual-access/single-cycle ram for increased memory-access performance: 512-byte instruction cache; 8k bytes of single-cycle dual-access program or data RAM; ROM-based boot loader supports program bootup using 8-, 16-, or 32-bit memories or one of the communication ports; (17)Software-communication-port reset; (18)NMI with bus-grant feature.

Diagrams